As field effect transistors (“FET”), such as PFETs and NFETs, are scaled down in size, semiconductor manufactures have utilized gate dielectrics having a high dielectric constant (“high-k”) to improve FET performance and reliability. High-k gate dielectrics are desirable in small feature size technologies since conventional gate dielectrics, such as silicon dioxide, are too thin and they result in high tunneling current, as well as other problems, which decrease performance and reliability of FETs. The FET also includes a gate electrode layer, which can be formed over the high-k gate dielectric layer. The gate electrode layer can comprise a conductive material such as doped polysilicon (“poly”), which is often used as a gate electrode material. However, when a poly gate electrode layer is formed over a high-k gate dielectric layer utilizing a conventional process, an undesirable interaction can occur between the poly gate electrode layer and the high-k dielectric layer, which can degrade the performance of the FET.
In a conventional process for fabricating a FET having a high-k gate dielectric and a poly gate electrode, a high-k dielectric, such as hafnium oxide or zirconium oxide, is formed over a channel region of a silicon substrate. Next, a layer of poly is deposited over the high-k dielectric layer typically utilizing a conventional precursor comprising silane (“SiH4”). However, an interaction can occur between the poly layer and the high-k material, such a hafnium oxide or zirconium oxide, which can degrade. the FET by causing high leakage between the poly gate electrode and the channel region of the substrate. According to one theory, the high leakage occurs as a result of hydrogen, which is released from the silane and which undesirably interacts with and reduces hafnium or zirconium in the high-k dielectric layer.
Thus, there is a need in the art for an effective method for forming a polysilicon gate electrode over a high-k dielectric in a FET.